1. Field of the Invention
The invention pertains to heat sinks for transistors of integrated circuits. In accordance with some embodiments, an integrated circuit (chip) includes at least one transistor terminal coupled to metal that provides a heat flow path from the transistor to bulk semiconductor material of the chip. The chip can be implemented by an SOI (silicon on insulator) process to include an insulator layer between the transistor and a substrate, the metal can extend through the insulator to the substrate, and the metal can be an interconnect produced by the same process step or steps performed to form other metal interconnects of the chip.
2. Description of the Related Art
The expression “PMOS transistor” herein denotes a P-channel MOSFET device. The expression “NMOS transistor” herein denotes an N-channel MOSFET device.
The term “N-well” herein denotes a well of N-type semiconductor material. The term “P-well” herein denotes a well of P-type semiconductor material.
The expressions “SOI chip” and “SOI integrated circuit” are used interchangeably herein to denote an integrated circuit implemented by a semiconductor on insulator (“SOI”) process. One type of SOI process includes the steps of bonding a first layer of silicon to an insulator (e.g., an oxide layer on a silicon substrate) and then performing processing steps to form a circuit in or on the first layer of silicon.
For many integrated circuits, one of the critical issues that significantly limits circuit capabilities is the self-heating effect. For example, in some SOI chips, undesirable self-heating of a transistor can occur under some operating conditions when heat generated in the transistor is not efficiently dissipated in the underlying semiconductor substrate because an electrically (and thermally) insulating layer (e.g., an oxide layer) between the transistor and substrate prevents efficient heat transfer from transistor to substrate. Self-heating can cause a variety of different undesirable effects. For example, transistors implemented in different areas of an SOI chip (e.g., transistors having identical structure) that are intended to operate with identical output current-voltage characteristics may actually have very different output current-voltage characteristics if they operate at significantly different temperatures. For another example, a current mirror implemented (using bipolar transistors) as an element of an SOI chip can generate an output current that that is not proportional to its input (reference) current as intended (i.e., the output current changes nonlinearly in response to changes in the input current) if the transistors operate at different temperatures.
Various integrated circuit structures have been proposed for providing transistor heat sinks. For example, U.S. Pat. No. 6,777,784, issued Aug. 17, 2004, and assigned to the assignee of the present invention, discloses a transistor (of an integrated circuit) having an enlarged metal terminal that can sink more heat from the rest of the transistor than could a smaller (conventionally-sized) terminal. Also, U.S. Pat. No. 6,777,784 and U.S. Pat. No. 6,407,445 (issued Jun. 18, 2002, and assigned to the assignee of the present invention) disclose a metal heat sink coupled to an element of a transistor (e.g., the base region of a bipolar transistor) for sinking heat from the transistor element to which the metal is coupled. However, neither reference suggests coupling the enlarged metal terminal (or separate metal heat sink) to bulk semiconductor material of the chip that includes the transistor.
U.S. Pat. No. 6,573,565, issued Jun. 3, 2003, discloses coupling a diamond-like (e.g., silicon carbide) or diamond structure to a transistor of an SOI chip. Each diamond (or diamond-like) structure provides a heat flow path from the transistor through a buried oxide layer (underlying the transistor) to a semiconductor substrate underlying the buried oxide layer, to allow heat from the transistor to dissipate in the substrate. Each diamond (or diamond-like) structure is said to be highly thermally conductive but electrically insulating. Disadvantageously, formation of such diamond (or diamond-like) structures would complicate the fabrication of conventional SOI chips (that do not include any other diamond or diamond-like structure) by requiring performance of at least one special process step in addition to the conventional processing steps performed to produce the chips' non-diamond (and non-diamond-like) structures.
U.S. Pat. No. 6,121,661, issued Sep. 19, 2000, discloses forming doped polysilicon plugs that extend from a transistor of an SOI chip (e.g., from the transistor's body) through buried oxide (underlying the transistor) to a semiconductor substrate underlying the buried oxide, to allow heat from the transistor to dissipate in the substrate. Each polysilicon plug is doped so as to have polarity opposite to that of the substrate material. Thus, there is a pn-junction at the plug-substrate boundary. Disadvantageously, formation of such heat-dissipating, doped polysilicon plugs would complicate the fabrication of conventional SOI chips (that do not include any other polysilicon structure sufficiently deep to extend from the top surface of their transistors' bodies through a buried oxide layer to an underlying substrate) by requiring performance of at least one special process step (a heat-dissipating, polysilicon plug-forming step) in addition to the conventional processing steps performed to produce the chips' other structures (i.e., the structures other than heat-dissipating polysilicon plugs). The polysilicon (“polygate layer”) employed to form the gates of conventional SOI chips conventionally has insufficient thickness to extend from the top of the transistor bodies of such a chip through the buried oxide layer to the underlying substrate. Thus, the processing steps performed to form the polygate layer of such chips could not also form heat-dissipating, doped polysilicon plugs of the type disclosed in U.S. Pat. No. 6,121,661. Rather, at least one additional processing step would be required to form such heat-dissipating, doped polysilicon plugs.